A floating-gate FET is a basic semiconductor device in which a floating-gate electrode (often simply “floating gate”) overlies a channel region that extends between a pair of source/drain regions. A control-gate electrode (often simply “control gate”) overlies the floating gate. In some floating-gate FETs such as the split-gate device described in U.S. Pat. No. 6,355,524 B1, another electrode commonly referred to as the select-gate electrode (often simply “select gate”) is situated to side of the floating and control gates above the channel region.
A floating-gate FET has a threshold voltage, referred to here as the programmable threshold voltage, which can be adjusted subsequent to FET manufacture for controlling the FET's operational characteristics. During FET operation, one of the source/drain regions functions as the source while the other functions as the drain. A control voltage is applied between the control gate and the source. With suitable potentials applied to other parts of the FET, the programmable threshold voltage is the value of the control voltage at which the FET switches between on and off conditions.
Floating-gate FETs are commonly employed as memory elements in EPROMs. The storage of information in a floating-gate memory FET is controlled by variously placing charge carriers on, and removing charge carriers from, the floating gate to adjust the FET's programmable threshold voltage. These two actions are generally referred to as “programming” and “erasure”. In a flash EPROM, all of the memory elements in a substantial portion of the EPROM are erased simultaneously.
Erasure in a flash EPROM formed with n-channel floating-gate FET memory elements is commonly performed by placing the body region of each memory FET at a suitable voltage relative to the FET's control gate. Electrons then tunnel from the floating gate through underlying insulating material to the channel region or/and the source. More particularly, erasure commonly entails (a) first raising the voltage applied to the body region to a suitably high value while the voltage applied to the control gate is reduced to a suitably low value to implement the erasure and (b) subsequently discharging these two voltages to an intermediate value or values. Erasure must be performed carefully to avoid damaging the EPROM.